1. Field
This disclosure relates generally to an integrated circuit and, more specifically, to power supply current spike reduction techniques for an integrated circuit.
2. Related Art
Today, the trend in clock design for relatively large integrated circuits (chips) has been to implement relatively low clock skew for all clock islands (i.e., logic blocks in different clock domains) of a chip. As clock skew reduces available cycle time, lower clock skew has generally provided better chip performance. Clock skew targets of ten picoseconds or less are common in clock designs with cycle times of two-hundred fifty picoseconds or less. However, achieving clocks skews of ten picoseconds or less across an entire chip can be relatively challenging. Moreover, power integrity, power consumption, decoupling capacitor real estate, packaging cost, back-end-of-line (BEOL) grid (i.e., interconnects and vias) cost, and schedule goals may be difficult to attain in chips that are designed to maintain clock skews of ten picoseconds or less across an entire chip. For example, maintaining relatively low clock skew across an entire chip may cause relatively large chips to generate relatively large current spikes (e.g., 920 amperes/nanosecond), which may lead to relatively large power supply voltage droops (e.g., power supply voltage droops of ten to twenty percent). In a known input/output (I/O) design approach, clock skew has been intentionally introduced between I/O buffers associated with an I/O bus in an attempt to reduce interference between adjacent signal paths.
Power supply voltage droop generally causes loss of performance (due to increased circuit delay) if a power supply voltage is not raised to compensate for the voltage droop or relatively high power dissipation results if the power supply voltage is raised to compensate for the voltage droop. Moreover, power supply overshoot (attributable to package inductance) can cause reliability and/or functional issues with noise-susceptible circuitry, such as memory arrays and analog circuits. Known solutions used to mitigate power issues associated with relatively large current spikes include dedicating on-chip real estate (typically about ten percent) to thin-oxide decoupling capacitor cells and/or employing deep-trench capacitors within a chip.
However, on-chip decoupling capacitors are relatively expensive and may lead to decreased integrated circuit yield, due to failure of the on-chip decoupling capacitors. Moreover, even near-ideal on-die power supply decoupling may not satisfy all current spikes, which can exceed one-hundred forty amperes. Additionally, addressing current spikes attributable to reduced clock skew generally also increases first-level and second-level packaging costs. For example, exotic packages (e.g., glass on ceramic) and discrete surface mount technology (SMT) capacitors may be employed to mitigate current spikes. Unfortunately, exotic packages are relatively expensive and discrete SMT capacitors tend to be cumbersome to install. For example, locating package decoupling capacitors close to a chip (e.g., underneath a die) has led to more expensive designs in which one or more holes have been provided in an associated printed circuit board (or card). While high-frequency low-inductance chip array (LICA) capacitors may be implemented off-chip to address current spikes, implementing LICA capacitors off-chip is relatively expensive and may be cost prohibitive for many designs.